General Circuit and Logic Design Concerns

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Weaknesses in this category are related to hardware-circuit design and logic (e.g., CMOS transistors, finite state machines, and registers) as well as issues related to hardware description languages such as System Verilog and VHDL.

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• CWE-1209 Failure to Disable Reserved Bits
• CWE-1221 Incorrect Register Defaults or Module Parameters
• CWE-1223 Race Condition for Write-Once Attributes
• CWE-1224 Improper Restriction of Write-Once Bit Fields
• CWE-1231 Improper Prevention of Lock Bit Modification
• CWE-1232 Improper Lock Behavior After Power State Transition
• CWE-1233 Security-Sensitive Hardware Controls with Missing Lock Bit Protection
• CWE-1234 Hardware Internal or Debug Modes Allow Override of Locks
• CWE-1245 Improper Finite State Machines (FSMs) in Hardware Logic
• CWE-1250 Improper Preservation of Consistency Between Independent Representations of Shared State
• CWE-1253 Incorrect Selection of Fuse Values
• CWE-1254 Incorrect Comparison Logic Granularity
• CWE-1261 Improper Handling of Single Event Upsets
• CWE-1298 Hardware Logic Contains Race Conditions