Hardware Logic Contains Race Conditions

Opis

A race condition in the hardware logic results in undermining security guarantees of the system.

A race condition in logic circuits typically occurs when a logic gate gets inputs from signals that have traversed different paths while originating from the same source. Such inputs to the gate can change at slightly different times in response to a change in the source signal. This results in a timing error or a glitch (temporary or permanent) that causes the output to change to an unwanted state before settling back to the desired state. If such timing errors occur in access control logic or finite state machines that are implemented in security sensitive flows, an attacker might exploit them to circumvent existing protections.

Skutki

• Access Control

  Bypass Protection Mechanism; Gain Privileges or Assume Identity; Alter Execution Logic

Zapobieganie

• Architecture and Design

  Adopting design practices that encourage designers to recognize and eliminate race conditions, such as Karnaugh maps, could result in the decrease in occurrences of race conditions.

• Implementation

  Logic redundancy can be implemented along security critical paths to prevent race conditions. To avoid metastability, it is a good practice in general to default to a secure state in which access is not given to untrusted agents.

Słabość nadrzędna

• CWE-362 Concurrent Execution using Shared Resource with Improper Synchronization ('Race Condition')

Kiedy powstaje

• Architecture and Design
• Implementation

Dotyczy

Verilog, VHDL, System on Chip

Źródła

1. FPGA designs with Verilog (section 7.4 Glitches) — Meher Krishna Patel
2. Non-Blocking Assignments in Verilog Synthesis, Coding Styles that Kill! — Clifford E. Cummings, 2000
3. dma.sv — 2021
4. Fix for dma.sv — 2021