Incorrect Register Defaults or Module Parameters

Opis

Hardware description language code incorrectly defines register defaults or hardware Intellectual Property (IP) parameters to insecure values.

Integrated circuits and hardware IP software programmable controls and settings are commonly stored in register circuits. These register contents have to be initialized at hardware reset to defined default values that are hard coded in the hardware description language (HDL) code of the hardware unit. Hardware descriptive languages also support definition of parameter variables, which can be defined in code during instantiation of the hardware IP module. Such parameters are generally used to configure a specific instance of a hardware IP in the design.

The system security settings of a hardware design can be affected by incorrectly defined default values or IP parameters. The hardware IP would be in an insecure state at power reset, and this can be exposed or exploited by untrusted software running on the system. Both register defaults and parameters are hardcoded values, which cannot be changed using software or firmware patches but must be changed in hardware silicon. Thus, such security issues are considerably more difficult to address later in the lifecycle. Hardware designs can have a large number of such parameters and register defaults settings, and it is important to have design tool support to check these settings in an automated way and be able to identify which settings are security sensitive.

Skutki

• Confidentiality, Integrity, Availability, Access Control

  Varies by Context

  Degradation of system functionality, or loss of access control enforcement can occur.

Zapobieganie

• Architecture and Design

  During hardware design, all the system parameters and register defaults must be reviewed to identify security sensitive settings.

• Implementation

  The default values of these security sensitive settings need to be defined as part of the design review phase.

Słabość nadrzędna

• CWE-1419 Incorrect Initialization of Resource

Kiedy powstaje

• Implementation — Such issues could be introduced during implementation of hardware design, since IP parameters and defaults are defined in HDL code and identified later during Testing or System Configuration phases.

Dotyczy

Verilog, VHDL, Not Technology-Specific

Źródła

1. fuse_mem.sv — 2021
2. fix CWE 1221 in fuse_mem.sv — 2021
3. acct_wrapper.sv — 2021
4. Bad Code acct_wrapper.sv — 2021
5. Good Code acct_wrapper.sv — 2021