Improper Handling of Faults that Lead to Instruction Skips

Opis

The device is missing or incorrectly implements circuitry or sensors that detect and mitigate the skipping of security-critical CPU instructions when they occur.

The operating conditions of hardware may change in ways that cause unexpected behavior to occur, including the skipping of security-critical CPU instructions. Generally, this can occur due to electrical disturbances or when the device operates outside of its expected conditions.

In practice, application code may contain conditional branches that are security-sensitive (e.g., accepting or rejecting a user-provided password). These conditional branches are typically implemented by a single conditional branch instruction in the program binary which, if skipped, may lead to effectively flipping the branch condition - i.e., causing the wrong security-sensitive branch to be taken. This affects processes such as firmware authentication, password verification, and other security-sensitive decision points.

Attackers can use fault injection techniques to alter the operating conditions of hardware so that security-critical instructions are skipped more frequently or more reliably than they would in a "natural" setting.

Skutki

• Confidentiality, Integrity, Authentication

  Bypass Protection Mechanism; Alter Execution Logic; Unexpected State

  Depending on the context, instruction skipping can have a broad range of consequences related to the generic bypassing of security critical code.

Zapobieganie

• Architecture and Design

  Design strategies for ensuring safe failure if inputs, such as Vcc, are modified out of acceptable ranges.

• Architecture and Design

  Design strategies for ensuring safe behavior if instructions attempt to be skipped.

• Architecture and Design

  Identify mission critical secrets that should be wiped if faulting is detected, and design a mechanism to do the deletion.

• Implementation

  Add redundancy by performing an operation multiple times, either in space or time, and perform majority voting. Additionally, make conditional instruction timing unpredictable.

• Implementation

  Use redundant operations or canaries to detect and respond to faults.

• Implementation

  Ensure that fault mitigations are strong enough in practice. For example, a low power detection mechanism that takes 50 clock cycles to trigger at lower voltages may be an insufficient security mechanism if the instruction counter has already progressed with no other CPU activity occurring.

Przykłady podatności

• CVE-2019-15894 fault injection attack bypasses the verification mode, potentially allowing arbitrary code execution.

Słabość nadrzędna

• CWE-1384 Improper Handling of Physical or Environmental Conditions

Pokrewna

• CWE-1247 Improper Protection Against Voltage and Clock Glitches

Kiedy powstaje

• Architecture and Design — Failure to design appropriate countermeasures to common fault injection techniques can manifest this weakness.
• Implementation — This weakness can arise if the hardware design incorrectly implements countermeasures to prevent fault injection.

Dotyczy

Not Language-Specific, Not OS-Specific, Not Architecture-Specific, System on Chip

Źródła

1. An In-depth and Black-box Characterization of the Effects of Clock Glitches on 8-bit MCUs — Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede, 2011 Workshop on Fault Diagnosis and Tolerance in Cryptography (IEEE), 2011
2. Experimental Analysis of the Electromagnetic Instruction Skip Fault Model — Alexandre Menu, Jean-Max Dutertre, Olivier Potin, Jean-Baptiste Rigaud, IEEE Xplore, 2020
3. Controlling PC on ARM using Fault Injection — Niek Timmers, Albert Spruyt, Marc Witteman, 2016
4. Attacking USB Gear with EMFI — Colin O'Flynn, Circuit Cellar, 2019
5. On The Susceptibility of Texas Instruments SimpleLink Platform Microcontrollers to Non-Invasive Physical Attacks — Lennert Wouters, Benedikt Gierlichs, Bart Preneel, 4.3, 2022