Improper Protection Against Voltage and Clock Glitches

Opis

The device does not contain or contains incorrectly implemented circuitry or sensors to detect and mitigate voltage and clock glitches and protect sensitive information or software contained on the device.

A device might support features such as secure boot which are supplemented with hardware and firmware support. This involves establishing a chain of trust, starting with an immutable root of trust by checking the signature of the next stage (culminating with the OS and runtime software) against a golden value before transferring control. The intermediate stages typically set up the system in a secure state by configuring several access control settings. Similarly, security logic for exercising a debug or testing interface may be implemented in hardware, firmware, or both. A device needs to guard against fault attacks such as voltage glitches and clock glitches that an attacker may employ in an attempt to compromise the system.

Skutki

• Confidentiality, Integrity, Availability, Access Control

  Gain Privileges or Assume Identity; Bypass Protection Mechanism; Read Memory; Modify Memory; Execute Unauthorized Code or Commands

Zapobieganie

• Architecture and Design, Implementation

  At the circuit-level, using Tunable Replica Circuits (TRCs) or special flip-flops such as Razor flip-flops helps mitigate glitch attacks. Working at the SoC or platform base, level sensors may be implemented to detect glitches. Implementing redundancy in security-sensitive code (e.g., where checks are performed)also can help with mitigation of glitch attacks.

Przykłady podatności

• CVE-2019-17391 Lack of anti-glitch protections allows an attacker to launch a physical attack to bypass the secure boot and read protected eFuses.
• CVE-2021-33478 IP communication firmware allows access to a boot shell via certain impulses

Słabość nadrzędna

• CWE-1384 Improper Handling of Physical or Environmental Conditions

Kiedy powstaje

• Operation

Dotyczy

Not Language-Specific, Not OS-Specific, Not Architecture-Specific, ICS/OT, System on Chip, Power Management Hardware, Clock/Counter Hardware, Sensor Hardware

Źródła

1. Circuit Techniques for Dynamic Variation Tolerance — Keith Bowman, James Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Borkar
2. Razor: A Low-Power Pipeline Based on Circuit-Level Timing Speculation — Dan Ernst, Nam Sung Kim, Shidhartha Das, Sanjay Pant, Rajeev Rao, Toan Pham, Conrad Ziesler, David Blaauw, Todd Austin, Krisztian Flautner, Trevor Mudge
3. Tunable Replica Circuits and Adaptive Voltage-Frequency Techniques for Dynamic Voltage, Temperature, and Aging Variation Tolerance — James Tschanz, Keith Bowman, Steve Walstra, Marty Agostinelli, Tanay Karnik, Vivek De
4. FAME: Fault-attack Aware Microprocessor Extensions for Hardware Fault Detection and Software Fault Response — Bilgiday Yuce, Nahid F. Ghalaty, Chinmay Deshpande, Conor Patrick, Leyla Nazhandali, Patrick Schaumont
5. A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance — Keith A. Bowman, James W. Tschanz, Shih-Lien L. Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris B. Wilkerson, Tanay Karnik, Vivek De
6. Bypassing Secure Boot Using Fault Injection — Niek Timmers, Albert Spruyt
7. Security Engineering — Ross Anderson, 14.6.2 Security Evolution, page 291, 2001
8. Security Engineering — Ross Anderson, 15.5.3 Glitching, page 317, 2001
9. Plundervolt — Kit Murdock, David Oswald, Flavio D Garcia, Jo Van Bulck, Frank Piessens, Daniel Gruss
10. CLKSCREW: Exposing the Perils of Security-Oblivious Energy Management — Adrian Tang, Simha Sethumadhavan, Salvatore Stolfo
11. Physical Security Attacks Against Silicon Devices — Texas Instruments, 2022
12. On The Susceptibility of Texas Instruments SimpleLink Platform Microcontrollers to Non-Invasive Physical Attacks — Lennert Wouters, Benedikt Gierlichs, Bart Preneel, 1.2 / 4, 2022