Driving Intermediate Cryptographic State/Results to Hardware Module Outputs

Opis

The product uses a hardware module implementing a cryptographic algorithm that writes sensitive information about the intermediate state or results of its cryptographic operations via one of its output wires (typically the output port containing the final result).

Skutki

• Confidentiality

  Read Memory; Read Application Data

  Mathematically sound cryptographic algorithms rely on their correct implementation for security. These assumptions might break when a hardware crypto module leaks intermediate encryption states or results such that they can be observed by an adversary. If intermediate state is observed, it might be possible for an attacker to identify the secrets used in the cryptographic operation.

Zapobieganie

• Architecture and Design

  Designers/developers should add or modify existing control flow logic along any data flow paths that connect "sources" (signals with intermediate cryptographic state/results) with "sinks" (hardware module outputs and other signals outside of trusted cryptographic zone). The control flow logic should only allow cryptographic results to be driven to "sinks" when appropriate conditions are satisfied (typically when the final result for a cryptographic operation has been generated). When the appropriate conditions are not satisfied (i.e., before or during a cryptographic operation), the control flow logic should drive a safe default value to "sinks".

  Skuteczność: High

• Implementation

  Designers/developers should add or modify existing control flow logic along any data flow paths that connect "sources" (signals with intermediate cryptographic state/results) with "sinks" (hardware module outputs and other signals outside of trusted cryptographic zone). The control flow logic should only allow cryptographic results to be driven to "sinks" when appropriate conditions are satisfied (typically when the final result for a cryptographic operation has been generated). When the appropriate conditions are not satisfied (i.e., before or during a cryptographic operation), the control flow logic should drive a safe default value to "sinks".

  Skuteczność: High

Słabość nadrzędna

• CWE-200 Exposure of Sensitive Information to an Unauthorized Actor

Pokrewna

• CWE-497 Exposure of Sensitive System Information to an Unauthorized Control Sphere

Kiedy powstaje

• Implementation — This can occur when intermediate cryptographic states are directly assigned to output wires or ports.

Dotyczy

Not Language-Specific, Not Architecture-Specific, System on Chip

Źródła

1. OpenTitan issue: [otp_ctrl] Prevent broadcast of scrambler's input/intermediate values #13043 — Andres Meza, 2022
2. Security Verification of the OpenTitan Hardware Root of Trust — Andres Meza, Francesco Restuccia, Jason Oberg, Dominic Rizzo, Ryan Kastner, 2023
3. Security Verification of an Open Source Hardware Root of Trust — Jason Oberg, 2022
4. Complete reverse-engineering of AES-like block ciphers by SCARE and FIRE attacks — Christophe Clavier, Quentin Isorez, Damien Marion, Antoine Wurcker, 2014
5. Practical Reverse Engineering of Secret Sboxes by Side-Channel Analysis — Dirmanto Jap, Shivam Bhasin, 2020