Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution

Opis

A processor event may allow transient operations to access architecturally restricted data (for example, in another address space) in a shared microarchitectural structure (for example, a CPU cache), potentially exposing the data over a covert channel.

Many commodity processors have Instruction Set Architecture (ISA) features that protect software components from one another. These features can include memory segmentation, virtual memory, privilege rings, trusted execution environments, and virtual machines, among others. For example, virtual memory provides each process with its own address space, which prevents processes from accessing each other's private data. Many of these features can be used to form hardware-enforced security boundaries between software components.

Many commodity processors also share microarchitectural resources that cache (temporarily store) data, which may be confidential. These resources may be shared across processor contexts, including across SMT threads, privilege rings, or others.

When transient operations allow access to ISA-protected data in a shared microarchitectural resource, this might violate users' expectations of the ISA feature that is bypassed. For example, if transient operations can access a victim's private data in a shared microarchitectural resource, then the operations' microarchitectural side effects may correspond to the accessed data. If an attacker can trigger these transient operations and observe their side effects through a covert channel [REF-1400], then the attacker may be able to infer the victim's private data. Private data could include sensitive program data, OS/VMM data, page table data (such as memory addresses), system configuration data (see Demonstrative Example 3), or any other data that the attacker does not have the required privileges to access.

Skutki

• Confidentiality

  Read Memory

  <<put the information here>>

Zapobieganie

• Architecture and Design

  Hardware designers may choose to engineer the processor's pipeline to prevent architecturally restricted data from being used by operations that can execute transiently.

  Skuteczność: High

• Architecture and Design

  Hardware designers may choose not to share microarchitectural resources that can contain sensitive data, such as fill buffers and store buffers.

  Skuteczność: Moderate

• Architecture and Design

  Hardware designers may choose to sanitize specific microarchitectural state (for example, store buffers) when the processor transitions to a different context, such as whenever a system call is invoked. Alternatively, the hardware may expose instruction(s) that allow software to sanitize microarchitectural state according to the user or system administrator's threat model. These mitigation approaches are similar to those that address CWE-226; however, sanitizing microarchitectural state may not be the optimal or best way to mitigate this weakness on every processor design.

  Skuteczność: Moderate

• Architecture and Design

  The hardware designer can attempt to prevent transient execution from causing observable discrepancies in specific covert channels.

  Skuteczność: Limited

• Architecture and Design

  Software architects may design software to enforce strong isolation between different contexts. For example, kernel page table isolation (KPTI) mitigates the Meltdown vulnerability [REF-1401] by separating user-mode page tables from kernel-mode page tables, which prevents user-mode processes from using Meltdown to transiently access kernel memory [REF-1404].

  Skuteczność: Limited

• Build and Compilation

  If the weakness is exposed by a single instruction (or a small set of instructions), then the compiler (or JIT, etc.) can be configured to prevent the affected instruction(s) from being generated, and instead generate an alternate sequence of instructions that is not affected by the weakness.

  Skuteczność: Limited

• Build and Compilation

  Use software techniques (including the use of serialization instructions) that are intended to reduce the number of instructions that can be executed transiently after a processor event or misprediction.

  Skuteczność: Incidental

• Implementation

  System software can mitigate this weakness by invoking state-sanitizing operations when switching from one context to another, according to the hardware vendor's recommendations.

  Skuteczność: Limited

• System Configuration

  Some systems may allow the user to disable (for example, in the BIOS) sharing of the affected resource.

  Skuteczność: Limited

• System Configuration

  Some systems may allow the user to disable (for example, in the BIOS) microarchitectural features that allow transient access to architecturally restricted data.

  Skuteczność: Limited

• Patching and Maintenance

  The hardware vendor may provide a patch to sanitize the affected shared microarchitectural state when the processor transitions to a different context.

  Skuteczność: Moderate

• Patching and Maintenance

  This kind of patch may not be feasible or implementable for all processors or all weaknesses.

  Skuteczność: Limited

• Requirements

  Processor designers, system software vendors, or other agents may choose to restrict the ability of unprivileged software to access to high-resolution timers that are commonly used to monitor covert channels.

  Skuteczność: Defense in Depth

Przykłady podatności

• CVE-2017-5715 A fault may allow transient user-mode operations to access kernel data cached in the L1D, potentially exposing the data over a covert channel.
• CVE-2018-3615 A fault may allow transient non-enclave operations to access SGX enclave data cached in the L1D, potentially exposing the data over a covert channel.
• CVE-2019-1135 A TSX Asynchronous Abort may allow transient operations to access architecturally restricted data, potentially exposing the data over a covert channel.

Słabość nadrzędna

• CWE-1420 Exposure of Sensitive Information during Transient Execution

Kiedy powstaje

• Architecture and Design — This weakness can be introduced during hardware architecture and design if a data path allows architecturally restricted data to propagate to operations that execute before an older mis-prediction or processor event (such as an exception) is caught.
• Implementation — This weakness can be introduced during system software implementation if state-sanitizing operations are not invoked when switching from one context to another, according to the hardware vendor's recommendations for mitigating the weakness.
• System Configuration — This weakness can be introduced if the system has not been configured according to the hardware vendor's recommendations for mitigating the weakness.
• Architecture and Design — This weakness can be introduced when an access control check (for example, checking page permissions) can proceed in parallel with the access operation (for example, a load) that is being checked. If the processor can allow the access operation to execute before the check completes, this race condition may allow subsequent transient operations to expose sensitive information.

Dotyczy

Not Language-Specific, Not OS-Specific, Not Architecture-Specific, Not Technology-Specific

Źródła

1. Page Table Isolation (PTI) — The kernel development community, 2023
2. RIDL: Rogue In-Flight Data Load — Stephan van Schaik, Alyssa Milburn, Sebastian Österlund, Pietro Frigo, Giorgi Maisuradze, Kaveh Razavi, Herbert Bos, Cristiano Giuffrida, 2019
3. Downfall: Exploiting Speculative Data Gathering — Daniel Moghimi, 2023
4. Hardware Security Leak Detection by Symbolic Simulation — Neta Bar Kama, Roope Kaivola, 2021
5. Meltdown: Reading Kernel Memory from User Space — Moritz Lipp, Michael Schwarz, Daniel Gruss, Thomas Prescher, Werner Haas, Stefan Mangard, Paul Kocher, Daniel Genkin, Yuval Yarom, Mike Hamburg, 2020
6. Microarchitectural Data Sampling — Intel Corporation, 2021
7. Cache Speculation Side-channels — ARM, 2018
8. Rogue System Register Read/CVE-2018-3640/INTEL-SA-00115 — Intel Corporation, 2018
9. Refined Speculative Execution Terminology — Intel Corporation, 2022
10. You Cannot Always Win the Race: Analyzing the LFENCE/JMP Mitigation for Branch Target Injection — Alyssa Milburn, Ke Sun, Henrique Kawakami, 2022
11. Medusa: Microarchitectural: Data Leakage via Automated Attack Synthesis — Daniel Moghimi, Moritz Lipp, Berk Sunar, Michael Schwarz, 2020
12. InvisiSpec: making speculative execution invisible in the cache hierarchy. — Mengjia Yan, Jiho Choi, Dimitrios Skarlatos, Adam Morrison, Christopher W. Fletcher, Josep Torrella, 2019
13. Port Contention for Fun and Profit — Alejandro Cabrera Aldaya, Billy Bob Brumley, Sohaib ul Hassan, Cesar Pereida García, Nicola Tuveri, 2019
14. Speculative Interference Attacks: Breaking Invisible Speculation Schemes — Mohammad Behnia, Prateek Sahu, Riccardo Paccagnella, Jiyong Yu, Zirui Zhao, Xiang Zou, Thomas Unterluggauer, Josep Torrellas, Carlos Rozas, Adam Morrison, Frank Mckeen, Fangfei Liu, Ron Gabor, Christopher W. Fletcher, Abhishek Basak, Alaa Alameldeen, 2021
15. Spectre is here to stay: An analysis of side-channels and speculative execution — Ross Mcilroy, Jaroslav Sevcik, Tobias Tebbi, Ben L. Titzer, Toon Verwaest, 2019