CWE-1278 · Słabość
Missing Protection Against Hardware Reverse Engineering Using Integrated Circuit (IC) Imaging Techniques
- Abstrakcja
- Bazowa
- Status
- Niekompletny
- Dodano
- 20 maja 2020
- Ostatnia zmiana
- 11 grudnia 2025
Opis
Information stored in hardware may be recovered by an attacker with the capability to capture and analyze images of the integrated circuit using techniques such as scanning electron microscopy.
The physical structure of a device, viewed at high enough magnification, can reveal the information stored inside. Typical steps in IC reverse engineering involve removing the chip packaging (decapsulation) then using various imaging techniques ranging from high resolution x-ray microscopy to invasive techniques involving removing IC layers and imaging each layer using a scanning electron microscope.
The goal of such activities is to recover secret keys, unique device identifiers, and proprietary code and circuit designs embedded in hardware that the attacker has been unsuccessful at accessing through other means. These secrets may be stored in non-volatile memory or in the circuit netlist. Memory technologies such as masked ROM allow easier to extraction of secrets than One-time Programmable (OTP) memory.
Skutki
Confidentiality
Varies by Context
A common goal of malicious actors who reverse engineer ICs is to produce and sell counterfeit versions of the IC.
Zapobieganie
Architecture and Design
The cost of secret extraction via IC reverse engineering should outweigh the potential value of the secrets being extracted. Threat model and value of secrets should be used to choose the technology used to safeguard those secrets. Examples include IC camouflaging and obfuscation, tamper-proof packaging, active shielding, and physical tampering detection information erasure.
Słabość nadrzędna
Kiedy powstaje
- Architecture and Design
Dotyczy
Not Language-Specific, Not OS-Specific, Not Architecture-Specific, Not Technology-Specific
Uwagi
This entry is still under development and will continue to see updates and content improvements. It is more attack-oriented, so it might be more suited for CAPEC.
Źródła
- A Survey on Chip to System Reverse Engineering — Shahed E. Quadir, Junlin Chen, Domenic Forte, Navid Asadizanjani, Sina Shahbazmohamadi, Lei Wang, John Chandy, Mark Tehranipoor
- Security Failures In Secure Devices — Christopher Tarnovsky, 2008
Wpis z katalogu CWE 4.20.