CWE-1272 · Słabość
Sensitive Information Uncleared Before Debug/Power State Transition
- Abstrakcja
- Bazowa
- Status
- Stabilny
- Dodano
- 31 maja 2020
- Ostatnia zmiana
- 9 września 2025
Opis
The product performs a power or debug state transition, but it does not clear sensitive information that should no longer be accessible due to changes to information access restrictions.
A device or system frequently employs many power and sleep states during its normal operation (e.g., normal power, additional power, low power, hibernate, deep sleep, etc.). A device also may be operating within a debug condition. State transitions can happen from one power or debug state to another. If there is information available in the previous state which should not be available in the next state and is not properly removed before the transition into the next state, sensitive information may leak from the system.
Skutki
Confidentiality, Integrity, Availability, Access Control, Accountability, Authentication, Authorization, Non-Repudiation
Read Memory; Read Application Data
Sensitive information may be used to unlock additional capabilities of the device and take advantage of hidden functionalities which could be used to compromise device security.
Zapobieganie
Architecture and Design, Implementation
During state transitions, information not needed in the next state should be removed before the transition to the next state.
Przykłady podatności
- CVE-2020-12926 Product software does not set a flag as per TPM specifications, thereby preventing a failed authorization attempt from being recorded after a loss of power.
Słabość nadrzędna
Może prowadzić do
Kiedy powstaje
- Architecture and Design
Dotyczy
VHDL, Verilog, Hardware Description Language, Not OS-Specific, Not Architecture-Specific, Not Technology-Specific
Źródła
- Understanding the Security of ARM Debugging Features — Zhenyu Ning, Fengwei Zhang, 2019 IEEE Symposium on Security and Privacy (SP), 2019
Wpis z katalogu CWE 4.20.