Improper Write Handling in Limited-write Non-Volatile Memories

Opis

The product does not implement or incorrectly implements wear leveling operations in limited-write non-volatile memories.

Non-volatile memories such as NAND Flash, EEPROM, etc. have individually erasable segments, each of which can be put through a limited number of program/erase or write cycles. For example, the device can only endure a limited number of writes, after which the device becomes unreliable. In order to wear out the cells in a uniform manner, non-volatile memory and storage products based on the above-mentioned technologies implement a technique called wear leveling. Once a set threshold is reached, wear leveling maps writes of a logical block to a different physical block. This prevents a single physical block from prematurely failing due to a high concentration of writes.

Skutki

• Availability

  DoS: Instability

  If wear leveling is improperly implemented, attackers may be able to programmatically cause the storage to become unreliable within a much shorter time than would normally be expected.

Zapobieganie

• Architecture and Design, Implementation, Testing

  Include secure wear leveling algorithms and ensure they may not be bypassed.

  Skuteczność: High

Słabość nadrzędna

• CWE-400 Uncontrolled Resource Consumption

Kiedy powstaje

• Architecture and Design
• Implementation

Dotyczy

Not Language-Specific, Not OS-Specific, Not Architecture-Specific, System on Chip, Memory Hardware, Storage Hardware

Źródła

1. Enhancing Lifetime and Security of PCM-Based Main Memory with Start-Gap Wear Leveling — Moinuddin Qureshi, Michele Franchescini, Vijayalakshmi Srinivasan, Luis Lastras, Bulent Abali, John Karidis
2. Bad Block Management in NAND Flash Memory — Micron